1. Field of the Invention
The present invention relates to an electronic packaging structure constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.
In the current technology the utilization of flip chips which are mounted on an organic substrate of electronic packaging modules is subject to a tendency of the module components to warp at lower temperatures subsequent to cooling down from the cure temperature of an underfill between the components, and during temperature cycling of the modular package. This warpage of the components such as the chips and substrate, is caused by the considerable differences in the coefficients of thermal expansion (CTE) between the essentially silicon material of the chips, which may possess a CTE of 3 ppm/° C., and that of the circuitized chip carrier or substrate which is normally basically consistent of an organic material or laminate such as an epoxy, possessing a CTE of approximately 18 ppm/° C. Moreover, the encountered warpage is also increased as a result of the extensive mechanical coupling between the components which is introduced through the use of the underfill encapsulation. Moreover, the bending stiffness of respectively the chip, underfill encapsulant and of the organic material forming the chip carrier or substrate, is also of an important consideration in determining the potential warpage of the module.
Extremely severe module warpage can readily result in chip cracking, solder mask and circuit line cracking, underfill delamination and the like rendering the electronic package subject to failure in operation. Thus, when the module is attached, for example, to a printed circuit board (PCB) through the employment of solder joints, extremely high extra loads through the solder joints are necessary in order to force the module to conform with the printed circuit board. This effect causes more stresses to be imparted to the solder joints, and may result in reliability problems for the electronic package. Inasmuch as, increasingly, organic packaging is employed in this technology, it is economically extremely important for module reliability and acceptance in the electronic packaging industry to be able to reduce the deleterious thermally-induced warpage which is encountered in producing the electronic packages having organic substrates or carriers mounting chips, such as flip chips, with bonding thereof through the interposition of thermally curable underfill adhesions.
2. Discussion of the Prior Art
Although consideration has been given to some extent in the technology to reducing stresses which are encountered between chips and organic substrates caused by thermal cyclings and differences in the coefficients of thermal expansion resulting in warpage and delamination between the components, these have not always been adequately successful in the treatment and elimination of this encountered problem.
Ishida et al. U.S. Pat. No. 4,868,634 (and counterpart EP O 294 015 B1) each relate to an arrangement of memory chips on a card which simplifies the connection to the wiring busses on the card. The primary problems solved by this prior art are to (1) eliminate the need for double sided wiring and plated through holes (PTHs) on a memory card with higher chip density, and/or (2) eliminate the need for large spaces between the chips when a single sided wiring configuration is used. The main benefits are to reduce the cost of the circuit card and/or to increase the memory chip density. The angled orientation of the chip allows simplified connection of the data busses to common locations on the chip and it is not the object of the prior art publications to reduce stress in the chip, underfill, laminate or ball grid arrays (BGAs) as in the present invention. In fact, because of the nature of the multiple chips on a large card with no BGA type attached, the stress would be similar for the angled and straight chip arrangements in this type of prior art construction, whereas the invention is different from these structures in that (1) the purpose of rotating the chip is to obtain a stress reduction, not wiring ease/cost and (2) the stress reduction is in the module/BGA structure and would not apply to the large memory card format.
Bonfeld U.S. Pat. No. 3,611,317 relates to an arrangement of chips and circuit lines on a memory card, whereby the chip is angled relative to the edge of the card. The angled orientation of the chip allows simplified connection of the data busses to common locations on the chip. The chip density can be increased by adding additional chips in the interstitial spaces in the array that are in the proper position to pick up the common buss lines that are running along the card. The purpose of the patent is for wiring simplification and increased chip density; and it is not the object thereof to reduce stress in the chip, underfill, laminate or BGAs as in the present invention. Because of the nature of the multiple chips on a large card with no BGA type attach, the stress would be similar for the angled and straight chip arrangements for this prior type of application, whereas contrastingly, the present invention is different from the patent in that (1) the purpose of rotating the chip is stress reduction, not wiring ease/cost and (2) the stress reduction is in the module/BGA structure and would not apply to a large memory card format.
Peter U.S. Pat. No. 6,188,582 B1 relates to a method of interconnecting a chip and substrate with a device which is an alternative to the solder ball connection. The device consists of an array of wires surrounded by a sheath that is oriented perpendicularly between the chip and substrate, with the two ends of the sheath being solder connected to the chip and substrate. However, the wires have a lower stiffness than a solder ball and can more easily bend, which reduces the stress between the chip and substrate due to the CTE mismatch. The chip is oriented with its side parallel to the substrate in this patent, and in which there is no mention of alternative orientations. In contrast, the present invention disclosure uses conventional materials, structures and processes to reduce the stress in the chip, underfill, laminate and BGA joints, whereby the reduced stress emanataes from the 45 degree chip orientation. The present invention differs from the patent in that (1) the invention uses a conventional module and BGA attach structure, materials and processes as opposed to a unique module to card attach structure/process, and (2) the stress reduction is derived from the chip orientation in the present disclosure while the chip orientation is not mentioned in the patent and is shown in a conventional non-rotated format.